20-EFT.WP.Metrology.TimeBase v1.0 | Chapter 4 — Timestamp Chains & Latency Budgeting

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Chapter 4 — Timestamp Chains & Latency Budgeting

One-line objective: Decompose the timestamp chain from physics to application, define a metrologically sound end-to-end latency & jitter budget, and provide a closed loop for calibration, compensation, and publication.

I. Scope & Objects

1. Objects & inputs
   • Chain & stages: sensor/ADC → FPGA/NCO → DMA/NIC → driver → kernel → userland → network/edge.
   • References & triggers: 1PPS/10 MHz, GNSS, PTP/NTP, sync pulses, and external t_ref.
   • Observations: staged timestamps {t_hw, t_drv, t_k, t_usr, t_net}, stage delays {d_phy, d_adc, d_fpga, d_dma, d_nic, d_k, d_usr}, and jitter {J_*}.
2. Outputs & artifacts
   • Latency & jitter budget: lat_mean, lat_p99, J_rms, J_pp, with per-stage contributions and covariances.
   • Mapping & compensation: ts = map( tau_mono; offset, skew ) - bias_chain.
   • Manifest & provenance: manifest.time.path.* with calibration values, budgets, measurement methods, and signature.

II. Terms & Variables

• Timestamps & stage delays: t_ref, t_hw, t_drv, t_k, t_usr, d_i (stage-i delay).
• Physical propagation: gamma(ell), n_eff(ell), c_ref, dual-form arrival time T_arr and delta_form.
• Jitter & uncertainty: J_rms, J_pp, u(x), U = k * u_c.
• Network clock: PTP servo outputs hat{offset}, hat{skew} with quality fields state, rms_err.
• Statistical window: Delta_t; modeling base tau_mono; published base ts.

III. Axioms P504- **

• P504-1 (Single measurement point): Define a single timestamp point and polarity (ingress/egress) for each stage to avoid cross-phase contamination.
• P504-2 (Explicit physics): When physical propagation is involved, compute T_arr with gamma(ell) and n_eff and record both formulations with delta_form.
• P504-3 (Additive decomposition): End-to-end latency is the sum of deterministic stage terms and random terms; under independence, sum variances for jitter.
• P504-4 (Time-base consistency): Evaluate all delay stats on tau_mono, publish on ts with offset/skew/J.
• P504-5 (Symmetry declaration): Any one-way inference from round-trip must state symmetry assumptions and an upper bound on asymmetry.
• P504-6 (Hardware first): In network/I/O scenarios, hardware timestamping (NIC/FPGA) is the primary probe; software timestamps are fallback with inflated uncertainty.
• P504-7 (Conservative budgeting): Publish lat_p99 as mu + z_0.99 * sigma_eff and record the synthesis method and correlation assumptions.
• P504-8 (Units & dimensions): All equations must pass unit/dim and check_dim validation.

IV. Minimal Equations S504- **

• S504-1 (Chain decomposition)
  t_usr = t_ref + ( ∑ d_i ) + epsilon，where i ∈ {phy, adc, fpga, dma, nic, drv, k, usr} and epsilon is residual noise.
• S504-2 (Jitter composition, independence)
  J_rms^2 ≈ ( ∑ J_i^2 )；with correlation matrix C, J_rms^2 = 1^T C 1。
• S504-3 (P99 budgeting)
  If lat ~ N( mu, sigma^2 ) or by large-sample approximation, lat_p99 ≈ mu + z_0.99 * sigma, with z_0.99 ≈ 2.33. For heavy tails, prefer quantile or EVT estimators.
• S504-4 (Physical propagation arrival, dual forms)
  T_arr = ( 1 / c_ref ) * ( ∫ n_eff d ell )；T_arr = ( ∫ ( n_eff / c_ref ) d ell )；
  delta_form = | ( 1 / c_ref ) * ( ∫ n_eff d ell ) - ( ∫ ( n_eff / c_ref ) d ell ) |。
• S504-5 (Round-trip & asymmetry)
  RTT = d_fwd + d_rev; with symmetry d_fwd ≈ d_rev, take d_fwd ≈ RTT / 2; upper bound | d_fwd - d_rev | ≤ asym_max.
• S504-6 (Software timestamp bias)
  bias_sw ≈ sched_delay + ctx_switch + irq_latency; publish U_sw via Bootstrap/Delta (see CrossStats Ch.5).
• S504-7 (Mapping & compensation)
  ts = map( tau_mono; offset, skew ) - ( d_known + bias_chain )，where d_known = ∑ d_i^const, bias_chain is from calibration.
• S504-8 (Queueing & backpressure approximation)
  If a segment is approximated as M/M/1 with load rho < 1, then W_q ≈ rho^2 / ( mu_svc * ( 1 - rho ) ); its variability contributes to J_q.

V. Metrology Flow M50-4 (Build Chain → Measure → Calibrate → Budget → Publish)

• Build chain & define probes
  Specify stage probes, edges, and time domains; enable NIC/FPGA hardware timestamps and anchor to Chapter 3 references.
• Calibrate physical segment
  With known L_gamma and medium parameters, estimate both T_arr forms; verify via loopback/reflectometry and record delta_form.
• Profile driver/kernel/user segments
  Use intrusive markers and perf/trace to collect {t_drv, t_k, t_usr}; estimate bias_sw and U_sw via bootstrap.
• Measure network segment
  Enable PTP HW timestamps; collect hat{offset}, hat{skew}, path_delay; measure both directions and publish asym_max.
• Compose jitter & budget
  Compute per-stage J_i and correlations; synthesize J_rms; form lat_p99 and safety margin per S504-3.
• Compensate & write-back
  Compute bias_chain; compensate ts; persist manifest.time.path and contract results; sign for release.

VI. Contracts & Assertions

• C50-41 (Probe completeness): {t_hw, t_drv, t_k, t_usr} exist and non_decreasing(t).
• C50-42 (Physical consistency): delta_form ≤ tol_Tarr, publish L_gamma and medium parameters.
• C50-43 (HW timestamp priority): hw_ts_coverage ≥ cov_min; shortfall marked fallback=sw with inflated U.
• C50-44 (P99 budget meets target): lat_p99 ≤ budget_p99, J_rms ≤ tol_jitter_rms, J_pp ≤ tol_jitter_pp.
• C50-45 (Round-trip asymmetry): asym_max ≤ tol_asym; otherwise roll back and gray-release.
• C50-46 (Dimensional checks): check_dim(expr)=pass for all **S504-*` expressions.
• C50-47 (Queue stability): when using S504-8, require rho ≤ rho_max and monitor W_q_p99 ≤ tol_wq.

VII. Implementation Bindings I50-4*

• trace_timestamp_chain(frame|sample) -> {t_ref, t_hw, t_drv, t_k, t_usr}
• measure_propagation(gamma, n_eff, c_ref, method) -> {T_arr_dual, delta_form}
• calibrate_hwts(nic|fpga, pps) -> bias_hw
• profile_sw_stack(tracer, window) -> {bias_sw, U_sw}
• estimate_asymmetry(two_way_stream) -> asym_max
• compose_latency_budget(stages, cov) -> {mu, sigma, lat_p99, J_rms, J_pp}
• compensate_ts(ds, bias_chain, map_params) -> ds'
• emit_timepath_manifest(results, policy) -> manifest.time.path
• Invariants: unique(TraceID); delta_form ≤ tol_Tarr; lat_p99 and J_rms reproducible against measurements.

VIII. Cross-References

• Time-base modeling & stability baseline: Chapter 2 P502-* / S502-*.
• Clocks & references, GPSDO discipline: Chapter 3 of this volume.
• Timeline & sync cleaning: Methods.Cleaning v1.0 Chapter 5.
• Path & dual arrival forms: Methods.Cleaning v1.0 Chapter 6.
• Statistical uncertainty & P99 synthesis: Methods.CrossStats v1.0 Chapters 4/5 and Appendix E.

IX. Quality Gauges & Risk Control

• Suggested SLI/SLOs
  lat_mean, lat_p95/p99, J_rms, J_pp, hw_ts_coverage, asym_max, delta_form_p99, rho, W_q_p99.
• Alerts & rollback
  Threshold tiers: warn (0.8× SLO), rate-limit (0.95× SLO), rollback (≥ 1.0× SLO). On HW TS failure, switch to fallback=sw and inflate U and lat_p99.
• Audit & traceability
  Persist measurement methods, instruments & firmware versions, map_params, bias_chain, asym_max, and hash_sha256(manifest.time.path).

Summary