36-EFT.WP.EDX.Current v1.0 | Chapter 7 — Boundary Conditions & Interfaces (I30-*)

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Chapter 7 — Boundary Conditions & Interfaces (I30-*)

I. Chapter Objectives & Structure

1. Objective: Standardize boundary conditions for devices/conductors/media and the numerical implementation interfaces; provide a binding from layout to physical paths; and define simulation–measurement alignment APIs that operationalize and validate S20-* / S40-* / S50-*.
2. Structure: I30-1 Interface continuity → I30-2 Layout–path binding → I30-3 Simulation–measurement alignment API.
3. Shared dialect (time-of-arrival, two equivalent forms; both must declare gamma(ell) and d ell, and record delta_form):
   • Constant factored out: T_arr = ( 1 / c_ref ) * ( ∫ n_eff d ell )
   • General form: T_arr = ( ∫ ( n_eff / c_ref ) d ell )

II. Variables & Units (new in this chapter)

• BC: boundary-condition set (normal/tangential continuity, sources, surface loss, etc.); units per included quantities.
• layout: netlist/layout description (nets, pins, conductor segments, stackup, constraints).
• path = { gamma_p(ell) }: family of physical paths (piecewise smooth), bi-directionally mapped to layout.
• anchors = { a_k }: alignment anchors (probes/ports/standards/timebase sync points).
• deemb: de-embedding matrix/operator (units consistent with port dimensions).
• sync: timebase/trigger synchronization metadata (SI units).

I30-1 Interface Continuity

Statement

• Current continuity: ( n · J_1 ) - ( n · J_2 ) = - ( ∂sigma_s / ∂t ); with no surface accumulation, ( n · J_1 ) = ( n · J_2 ).
• Power flux: ( n · ( S_1 - S_2 ) ) = - p_s, where p_s is the interface loss/injection term.
• Tension consistency: jumps of T_fil across the interface are incorporated via equivalent sources/losses in BC without violating S20-* local conservation; when crossing interfaces, path segments of gamma(ell) are C0-continuous.

Domain & Constraints

• Measurable material parameters and interface geometry; BC must fix the normal n; check_dim passes.

Falsifiability

• With netlist and materials fixed, altering only the interface treatment (plating/grounding/crimping) must lead to I/V/Z changes predicted by the continuity conditions. Otherwise, reject the BC setup or its domain (after excluding instrumentation/synchronization errors).

Compliance record (template)

BC:

current_normal: "( n · J1 ) - ( n · J2 ) = - ∂sigma_s/∂t"

power_flux: "( n · ( S1 - S2 ) ) = - p_s"

tension_consistency: "path segments across interface are C0; jump → equivalent sources"

check_dim: pass

I30-2 Layout–Path Binding

Statement

• Establish a bi-directional map layout ↔ gamma(ell): map conductor segments/vias/stackup/guards and dielectric stack to path segments and their measures; assign each gamma_p a weight w_p and segment-level n_eff.
• Binding requirements: make port/pin/probe locations explicit as anchors; for each path segment record material, geometry, neighboring boundaries, and constraints.

Domain & Constraints

• Paths are piecewise smooth; w_p ≥ 0 and Σ_p w_p ≤ 1; delta_form, gamma(ell), and d ell are mandatory in data records.

Falsifiability

• Keeping electrical parameters and materials fixed while changing only routing/guards/ground-return mappings must shift arg Z(omega) and |Z| in line with predicted ΔT_arr and w_p. Otherwise, reject the binding model or the path set.

Compliance record (template)

binding:

bind_id: "LAY2PATH-xxxx"

ports: ["P1","P2", ...]

anchors: [{id:"A1", type:"probe", pos:"..."}]

paths:

- id: "γ_main"

segments:

- {mat:"Cu", t_um:35, w_um:120, len_mm:10.2, layer:"L3", neigh:"GND_L2", n_eff: ..., notes:"..."}

weight: w_main

- id: "γ_side1"

segments: [...]

weight: w_side1

arrival:

form: "n_over_c" # or "one_over_c_times_n"

gamma: "explicit" # path stored

measure: "d_ell"

check_dim: pass

I30-3 Simulation–Measurement Alignment API

Statement

• Goal: Align numerical simulation outputs and experimental records under the same dialect, unifying port definition, de-embedding, timebase, and path correction. The aligned outputs must be directly consumable by S40-* / S50-* for kernel inversion and impedance mapping.

Interfaces & Workflow

1. Port harmonization
   Map simulation ports ports_sim to measurement ports ports_meas: map_ports(ports_sim, anchors).
2. De-embedding & baseline
   Apply deemb to both measurement and simulation fixtures; fix baseline_id: apply_deemb(data, deemb, baseline_id).
3. Timebase/synchronization
   Align sync (trigger/sampling/reference clocks), compensate Δt_sync: time_align(data, sync).
4. Path correction
   Correct T_arr and phase using binding records: path_correct(data, binding).
5. Consistency checks
   QA gates: check_dim, passivity (Re{Z}≥0), and K–K consistency.

Domain & Constraints

• Record versions and parameters for anchors, deemb, sync, and binding; all steps in a single unit system.

Falsifiability

• If, after steps 1–4, systematic residuals remain (e.g., non-linear-in-omega constant phase offsets or negative real parts), reject the alignment parameters or the binding/kernel settings.

API prototypes (template)

api:

- id: "I30-3.map_ports"

proto: "map_ports(ports_sim, anchors) -> ports_meas_ordered"

- id: "I30-3.apply_deemb"

proto: "apply_deemb(dataset, deemb, baseline_id) -> dataset"

- id: "I30-3.time_align"

proto: "time_align(dataset, sync) -> dataset"

- id: "I30-3.path_correct"

proto: "path_correct(dataset, binding) -> dataset"

qa_gates: ["check_dim","passivity(Re{Z}≥0)","K-K_consistency"]

III. Compliance Snippets (unified, copy-ready)

• Continuity & power: ( n · J_1 ) - ( n · J_2 ) = - ( ∂sigma_s / ∂t ); ( n · ( S_1 - S_2 ) ) = - p_s.
• Arrival recording: T_arr = ( ∫ ( n_eff / c_ref ) d ell ) ; delta_form="n_over_c"; path: gamma(ell); measure: d ell.
• Minimal binding record: bind_id, ports, anchors, paths{segments,weight}, arrival{form,gamma,measure}.
• Alignment QA: check_dim = pass; Re{Z_eft}≥0; K–K consistency passed.

IV. Correspondence & Degeneracy to Classical Framework

V. Cross-Chapter & Implementation Guidance

• Upstream dependencies: S20-* (conservation & conduction), S40-* (kernels & weights), S50-* (impedance mapping).
• Downstream links: I40-* (circuit-level binding & measurement stack), M10-* / M20-* (metrology chain & falsification).

VI. Chapter Summary
This chapter consolidates interface continuity, layout–path binding, and sim–meas alignment into I30-1…I30-3 under a unified dialect, fixing record fields, QA gates, and falsifiability criteria so that S20-* / S40-* / S50-* close the loop between theory and engineering practice at the same data/interface layer.