53-Model Card Template v1.0 | Chapter 11 — Resources & Performance (SLA/SLO/Throughput/Latency/Power)

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Chapter 11 — Resources & Performance (SLA/SLO/Throughput/Latency/Power)

I. Purpose & Scope

• Standardize measurement, modeling, validation, and publication of deployment resource models (CPU/GPU/MEM/IO/NET/Power) and performance metrics (SLA/SLO/throughput/latency/jitter/power/cost), enabling capacity planning, load-test baselines, regression monitoring, and compliant release.
• For path quantities (arrival time/phase), the text must explicitly show gamma(ell) and d ell, record delta_form ∈ {general, factored} on the data side; all formulas are parenthesized; publication requires p_dim = 1.0.

II. Prerequisites & Inputs

• Data & splits: align with Dataset Card Ch. 4/6/7/11 (Schema/Splits/QC/Bench).
• Training & weights: align with this volume Ch. 6 (train_config.yaml, best.ckpt, env snapshot).
• Coverage & covariance: unify with Error Budget Card (coverage ∈ {k, alpha, quantile}, Σ PD).
• Parameters & freshness: align with Parameter Card (freshness.policy, cov_group).
• Citations & versions: “volume + version + anchor (P/S/M/I)”, anchor coverage ≥ 90%.

III. Resource Model

• Resource vector: R = (cpu, gpu, mem, io, net, power); suggested units: cpu: core·s, gpu: sm·s, mem: GiB, io/net: MB/s, power: W.
• Queueing approx: stable region ρ = λ/μ < 1; M/M/1 latency E[W] ≈ ρ/(μ−λ); with parallelism k, μ_eff ≈ k·μ.
• Batch/stream trade-off: micro-batch window T_win = k/f_s; larger windows increase throughput but raise Latency_P95.
• Capacity backsolve: with peak λ_peak and target ρ_target, μ_req = λ_peak/ρ_target, map to R quotas.
• Energy & cost: P_avg, Energy/req, cost_per_K, R_cost (core·h/GPU·h).

IV. KPIs & Statistics

• Latency: Latency_P50/P95/P99 (s); Throughput: req/s or MB/s; Jitter: quantile spread or MAD.
• Availability: SLA/SLO (e.g., availability ≥ 99.9%, P95 latency ≤ target); Loss rate: loss_rate.
• Resources: ρ (utilization), mem_peak, io/net_util; Energy: P_avg / Energy/req.
• Quality coupling: Q_res, p_dim (=1), ε_flux (path conservation error).

V. Control & Path Forms

• Arrival (equivalent forms):
  T_arr = ( 1 / c_ref ) * ( ∫ n_eff d ell )
  T_arr = ( ∫ ( n_eff / c_ref ) d ell )
• Phase accumulation:
  Phi = ( 2π / λ_ref ) * ( ∫ n_eff d ell )

Align “time → path → phase” before evaluation/reporting; record delta_form; arrays len(gamma_ell)=len(d_ell)=len(n_eff)≥2.

VI. Load Testing & Regression

• Baseline flow: cold start → steady → peak pulses → recovery; record Latency_P95/Throughput/ρ/P_avg curves with intervals.
• Regression monitor: compare δ_latency/δ_throughput/δ_power/δ_cost vs prior with CIs; out-of-band triggers degrade/rollback.
• Elastic scaling: scale near ρ_target, record convergence time & cost; principle: stability first, efficiency next.

VII. Gate Mapping

• G1 Schema completeness (perf tables/contracts present); G2 Citation compliance (anchor coverage ≥ 90%);
• G3 Path conventions (path block complete; step compliant); G4 Dimensional closure (p_dim = 1.0, check_dim_report.json OK);
• G5 Freshness (clock_state="locked", τ_calib compliant); G6 Coverage consistency (k/alpha/quantile unified);
• G7 Covariance consistency (Σ PD & aligned with Error Budget); G8 Uniqueness & acyclicity (artifacts with checksum, lineage acyclic).
• Trigger S1–S5 to block release or tag [Restricted].

VIII. Machine-Readable Configs
A. perf_sla.yaml

version: "1.0.0"

objectives:

latency_p95_s: 0.200

availability: 0.999

throughput_rps: 1000

loss_rate_max: 0.001

q_res_max: 0.20

guards:

p_dim_req: 1.0

jitter_p95_s: 0.020

power_w_max: 180

B. capacity_plan.yaml

version: "1.0.0"

load: { lambda_peak_rps: 1500, rho_target: 0.70 }

service: { mu_per_core_rps: 50, parallelism: 24 }

derived: { mu_req_rps: 2143, cores_req: 43 }

C. perf_probes.yaml

version: "1.0.0"

probes:

- name: "latency_hist"; window_s: 60; export: "figs/latency_hist.pdf"

- name: "throughput_series"; window_s: 60; export: "figs/throughput_series.svg"

- name: "resource_util"; window_s: 60; export: "figs/resource_util.pdf"

- name: "power_trace"; window_s: 60; export: "figs/power_trace.pdf"

IX. Anti-Patterns & Fixes

• Anti: reporting mean latency only (no P95/P99) → Fix: add quantiles with windows & intervals.
• Anti: T_arr = ∫ n_eff / c_ref d ell (no parentheses) → Fix: parenthesized unified forms.
• Anti: cross-version comparisons under different load → Fix: hold or normalize λ, or include power analysis.
• Anti: missing energy/cost → Fix: report P_avg/energy_per_req/cost_per_K.
• Anti: releasing with p_dim < 1 under stress → Fix: trigger S1 to block and degrade/rollback.

X. Release & Layout

PTN_EXPORT/

configs/

perf_sla.yaml

capacity_plan.yaml

perf_probes.yaml

reports/

check_dim_report.json

validate_report.json

perf_summary.md

figs/

latency_hist.pdf

throughput_series.svg

resource_util.pdf

power_trace.pdf

report_manifest.yaml

SIGNATURE.asc

XI. Cross-References

• Dataset Card: Ch. 6 (Splits), Ch. 11 (Bench/Score).
• Error Budget Card: Ch. 8/9 (intervals & threshold mapping).
• Pipeline Card: Ch. 5 (Timebase/Sync/Buffering), Ch. 8 (Resources & Performance), Ch. 12 (Outputs & Release).
• This volume: Ch. 6 (Training), Ch. 7 (UQ), Ch. 10 (Deployment Interfaces).

XII. Checklist

• perf_sla.yaml / capacity_plan.yaml / perf_probes.yaml stored and consistent with logs.
• Path & performance figures dual-exported; axes with units, captions include see[]/version; path plots annotate Δell and delta_form.
• I70-dim_check passed, p_dim = 1.0; coverage/covariance aligned with Error Budget; /validate passed G1–G8.
• Baseline & regression reports complete (P95/P99, throughput, ρ, energy, cost + intervals); load & environment reproducible.
• Non-compliances tagged [Restricted] with remediations; anchor coverage ≥ 90%; artifacts signed with checksums.